The USC Viterbi School of Engineering is among the top tier engineering schools in the world. It counts 191 full-time tenure-track faculty members, 79 full-time teaching faculty, and 40 full-time research faculty. Home to the Information Sciences Institute (ISI), the School has been the recipient of many national centers, including two National Science Foundation Engineering Research Centers, a Department of Energy EFRC (Energy Frontiers Research Center), and the Department of Homeland Securityâs first University Center of Excellence, CREATE. Affiliated with the Alfred E. Mann Institute for Biomedical Engineering, the Institute for Creative Technologies and the USC Stevens Center for Innovation, the School is the host of the NSF Innovation Node Los Angeles. Research expenditures exceed $200 million annually. The School has 32 National Academy of Engineering members and 2017 was awarded the ASEE Presidentâs Award for its continuing efforts to âchange the conversationâ about engineering and develop a robust and diverse engineering pipeline.
The Ming Hsieh Department of Electrical and Computer Engineering is one of Southern California's major research institutions. The department has 60 tenure/tenure-track faculty, 300 undergraduate students, more than 1200 masterâs students, and more than 300 Ph.D. students. In the 2020 school year, research expenditures in the department exceeded $30M in direct costs. The department has received 4 Shannon Awards, 16 members of the National Academy of Engineering, and 39 recipients of the NSF Early Career Award.
Experienced Digital ASIC/Design engineer to collaborate with research teams of professors, graduate students and research staff to realize first-time successful ASICs in advanced (28nm to 5nm) CMOS process-technology nodes. You are expected to understand the system-level design-requirements, system-plus-chip architecture and lead all aspects of the Digital IC design, tape-out and validation effort. You will be in charge of all aspects of IC implementation including pre- and post-layout verification plus tape-out to the Foundry. You will be expected to contribute throughout all stages of the ASIC development process.
This is a great opportunity to work with leading researchers, expand oneâs skills and experience, and be part of a team that is at the forefront of technology innovation.
Collaborating with architects, logic design, and software engineers. Participating in Micro-architecture and code reviews. Writing and maintaining documentation and specifications Assisting with digital designs including IP blocks and DFT/DFD Behavioral Verilog simulation Performing RTL implementation, integration/insertion, Synthesis, Equivalency checking, Timing analysis and closure including defining constraints, Design Verification (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
Physical Chip Design and Verification
Place and Route (Cadence, Synopsys) LVS/DRC/LPE (Mentor tools) Post-layout Verification Chip Tape-out to Foundry
Post-silicon Validation and support
Providing bring-up and debug support (including DFT/DFD and associated RCA) during first silicon bring-up
Establishing and maintaining the digital design flow using Cadence, Synopsys and Mentor tools (plus others as required). Maintaining all Cad tools and compatibility with various Foundry PDKs Creating software, scripts and other support technology to enable successful creation of the items above
Successful candidates will demonstrate an outstanding ability to think effectively, coupled with excellent technical depth and breadth that are supplemented with professional experience. They will have a demonstrable ability to define and execute independent research programs. Candidates with both theoretical and applied interests are encouraged to apply.
EDUCATION AND QUALIFICATIONS
Minimum Masterâs Degree Electrical or Computer Engineering (Combined experience/education as substitute for minimum education)
5+ years of professional experience in the technical areas listed below.
Professional expertise in ASIC design, fabrication, packaging, assembly and testing
Demonstrable technical expertise in all the following technical areas:
ASIC Design flows and EDA methodologies
Well-developed ability to analyze specifications at the architecture and micro-architecture level to identify design improvements
Digital IC Design
Schematic entry and layout tools (e.g Composer/Virtuoso from Cadence)
Verilog/System Verilog or similar HDL/HVL, simulator and waveform debugging tools
DFT/DFD techniques (JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST etc.)
Synthesis, Equivalence Checking, Place-and-route
Block and chip-level Timing Closure
Solid Pre-layout and Post-layout verification
Experience with Post-silicon validation using lab equipment such as: logic, PCIe and network analyzers, Oscilloscopes and arbitrary waveform generators (AWGâs)
UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl)
Experience of collaborative research projects with partners in industry and academia is a plus.
Hands-on experience with large-scale commercial ASIC projects is a plus.
Familiarity with ARM processor cores and tools
Hands-on experience of PCIe interface
Synthesis, timing analysis, Partitioning and place and route for FPGA
Device-level and transistor-level concepts
Working knowledge of transistor and gate-level circuit simulation using any variant of Spice.
Comfortable with both Unix and Windows environments
SKILLS AND COMPETENCIES
Willingness and capacity to expand leadership and technical skills.
Demonstrated ability to learn new things quickly and grow into new roles.
Flexibility and ability to adapt quickly to new tasks/challenges.
Strong analytical and quantitative problem-solving ability.
Strong cross-functional skills.
Positive mindset, Team player.
Ability and capacity to act as a mentor for team members.
Excellent relationship skills.
Excellent oral and written English language skills whether native or non-native speaker.
USC is the leading private research university in Los Angeles—a global center for arts, technology and international business. With more than 47,500 students, we are located primarily in Los Angeles but also in various US and global satellite locations. As the largest private employer in Los Angeles, responsible for $8 billion annually in economic activity in the region, we offer the opportunity to work in a dynamic and diverse environment, in careers that span a broad spectrum of talents and skills across a variety of academic and professional schools and administrative units. As a USC employee and member of the Trojan Family—the faculty, staff, students, and alumni who make USC a great place to work—you will enjoy excellent benefits, including a variety of well-being programs designed to help individuals achieve work-life balance.