Research Programmer II - EDA Developer

USC’s Information Sciences Institute (ISI), a unit of the university’s Viterbi School of Engineering, is a world leader in the research and development of advanced artificial intelligence, information processing, computing, and communications technologies. ISI’s 400 faculty, professional staff and graduate students carry out extraordinary information sciences research at three distinct locations - Marina Del Rey, CA; Arlington, VA; and Waltham, MA.

*This position is based in Arlington, VA. Remote work options are available *

The Reconfigurable Computing Group (RCG) at ISI is a leader in disrupting and advancing the fields of front-end ASIC and FPGA design, computer architecture, and EDA tools. As an applied research lab, our work spans the creation and maturation of ideas from academic conception to applied research prototypes.

RCG staff can be found:

• Researching and developing toolsets to map AI algorithms directly to hardware,
• Optimizing full scale testing of billion transistor FPGAs to minimal runtime,
• Performing experiments on the International Space Station,
• Utilizing ISI’s MOSIS service to fabricate novel computer architectures.

Our success is based on investing in our staff through a culture centered on:

• Learning and idea generation,
• Transparent and constructive feedback, and
• Continual growth through contributing to, creating, and leading a research agenda.

We are looking for highly talented, motivated developers to perform research and development in the area of EDA CAD tools for custom hardware acceleration. Be a member of a high caliber team creating the world’s first customized accelerator for native Fully Homomorphic Encryption (FHE). Lead the development of complex custom EDA tools to perform design space exploration of FHE architectures over performance parameters. Be an active member of a fast-paced ASIC Development team supporting the full life cycle from functional architecture definition to physical implementation, verification, and tape-out. This position will also support efforts in design space exploration for efficient resource utilization and implementation of ASIC and FPGA designs, as well as, evaluation in terms of performance, power, and useability metrics.  Lead development while contributing to advanced research, collaborating with peers within the group and across ISI, and contributing to publications in top tier conferences.

Position specific JOB QUALIFICATIONS:

• Graduate degree or equivalent experience in Computer Engineering, Electrical Engineering, or Computer Science required.
• Five years of digital design experience for ASIC or FPGAs using Synopsys, Cadence, Xilinx or Intel CAD tools and commercial/academic cad flows.
• 3-5 years development experience (C++/Python) including demonstrable contributions to large-scale projects (commercial or open-source development).
• 3-5 years of Embedded systems development, including Linux kernel development, device drivers, cross-compilers, memory subsystems, and data transfer protocols.
• Solid understanding of CAD algorithms leveraging High-Level Languages, LLVM, and High-Level Synthesis targeting heterogenous hardware platforms to accelerate end-user development.
• Strong experience with embedded systems hardware/software co-design and design space exploration with heterogenous computing architectures.
• Experienced user of standard digital design tools such as Cadence Stratus, Genus, and Innovus or Synopsys Synphony, Design Compiler, and IC compiler.
• Ability to evaluate, apply, and mature published research to real-world problems at scale on prototype systems.
• Ability to handle Controlled Unclassified Information (CUI). Per U.S. government regulations, eligibility to handle CUI requires U.S. Citizenship

 Preferred Job Qualifications:

• 3-5 years of experiences developing and/or verifying embedded systems with custom ASIC or FPGAs.
• 3-5 years of experience using digital logic formal verification and/or model checking tools such as Synopsys Formality, Cadence Conformal, Synopsys VC Formal.
• Experience targeting 12nm or smaller fabrication nodes a significant plus.
• Understanding of Machine Learning toolkits (Keras/TensorFlow/PyTorch) with demonstrable contributions to their application across heterogeneous hardware systems, including training and inference.
• Previous publications, patents, or innovations related to CAD tool development, Homomorphic Encryption, Machine Learning, FPGA security, or FPGA architecture.
• Experience with software revision control systems such as Git, Mercurial, SVN, etc.

The University of Southern California values diversity and is committed to equal opportunity in employment.